A Sliding Memory Plane Array Processor

This paper describes a new mesh-connected SIMD architecture, called a Sliding Memory Plane (SIiM) Array Processor. On SIiM, the inter-processing element (inter-PE) communication, using the sliding memory plane, and the data input/output (I/O), using two U 0 planes, can occur without interrupting the PE’s, which greatly diminishes the communication and I/O overhead. SliM is unique in its ability to overlap inter-PE communication with computation, regardless of window size and shape and without using a coprocessor or an on-chip DMA controller. In addition, SliM uses four rather than eight links per PE to provide eight-way connectivity using the by-passing path, thus reducing the diagonal communication time and eliminating the necessity of diagonal links. The realization of these virtual links for diagonal communication without instruction overhead is another novel feature of SYM. An alternative method to achieve diagonal communication is to use two sliding memory plane shifts that can be overlapped with computation. The bypassing path can also accomplish nonlocal communication and broadcast. This paper illustrates the unique advantages of these inter-PE and diagonal communication schemes and proposes new parallel algorithms for image processing on SliM that have a zero or an O(1) communication complexity. With these salient features, SliM shows a significant performance improvement, illustrated with several tasks including the DARPA low level vision benchmarks. Index Tems-Computer architectures, computer vision, image processing, parallel architectures and algorithms, mesh-connected SIMD machines, VLSI architectures, VLSI design.